In the 1960's, it was discovered that it was not possible to make a device that transferred data perfectly between two independent clock domains. Although it was possible to make the probability of failure arbitrarily small, it was not possible to make the probability zero. Many attempts were made to design a perfect synchronizer (e.g., using a flip flop to attempt to produce a signal that never enters a metastable state when the receiving system latched the data), but they all had a flaw lurking somewhere. The news of this fundamental problem was slow to spread through the industry so many commercial computer systems were produced that suffered from synchronizer failures.
Mead and Conway in the 1980 text, “Introduction to VLSI Systems,” describe ring oscillators or delay-based clocks that can be started at an arbitrary instant and interface well with asynchronous systems (such as that illustrated on pages 235 and 258). Two subsystems with such clocks can carry out the transfer of data without the requirement for synchronization, and thus be free of any synchronizer failure. This is accomplished by an asynchronous layer between the two subsystems such that the two systems are no longer completely independent. However, delay-based clocks suffer from variations in their periods as a result of temperature changes, process differences and noise. These variations led to worst case designs that run much slower than equivalent crystal clock designs. Unfortunately, traditional crystal clocks cannot be started at an arbitrary instant in time. Thus, this approach to interfacing asynchronous and synchronous system never gained favor.
In 1988, one of the inventors of this present patent application, designed a crystal clock that could be started and stopped using two multipliers carrying out a fundamental trigonometric identity, which was described in the published paper: Jerome R. Cox, Jr., “Can a Crystal Clock be Started and Stopped?” Applied Mathematics Letters, Vol., 1, Pergamon, pp. 37-40, which is hereby incorporated by reference in its entirety. As described therein, a stoppable crystal clock can be based on the synthesis of a sinusoid of arbitrary phase from two sinusoids whose phases are separated by ninety degrees. A crystal oscillator can produce the waveforms of sinωt and cosωt. If these waveforms are sampled at a time u, then a synthesized sinusoid s(t) with phase origin at time u can be obtained through use of the simple trigonometric identity:s(t)=cosωu·sinωt−sinωu·cosωt=sin(t−u)A square clock signal can be produced from the sign, sgn(s(t)), of this waveform. The positive-going zero crossings of this waveform occur precisely at multiples of the crystal-clock period after the arbitrary time u.
The stoppable crystal clock illustrated in this paper is reproduced herein as FIG. 1. This stoppable crystal clock uses a dual sample and hold element and two multipliers, a comparator, and an OR gate to generate a clock signal in response to a control signal. When this control signal, called the pause signal, is asserted, the clock stops before the next zero crossing and starts it again immediately upon removal of the pause signal. Even today, the dual sample and hold element does not allow the clock to operate at speeds required of systems. As stated in the article, it was “not clear that this design is practical and useful,” and “[p]erhaps as a result of the limited range of applications, or insignificant performance gains over delay-based stoppable clocks, crystal-based stoppable clocks may never find practical used.” These statements apparently were true as there has been no known use or implementation of this design, despite the passing of approximately two and one half decades, and despite the great need in the computer and communications industries for a reliable restartable clock.